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mc145220 motorola wireless semiconductor solutions device data 1
" ! !" bicmos the mc145220 is a lowvoltage, singlechip frequency synthesizer with serial interface capable of direct usage up to 1.1 ghz. the device simulta- neously supports two loops. the two onchip dualmodulus prescalers may be independently programmed to divide by either 32/33 or 64/65. the device consists of two dualmodulus prescalers, two 6stage a counters, two 12stage n counters, two fully programmable 13stage r (reference) counters, and two lock detectors. four phase/frequency detectors are included: two with current source/sink outputs and two with doubleended outputs. the counters are programmed via a synchronous serial port which is spi compatible. the serial port is byteoriented to facilitate control via an mcu. due to the innovative bitgrabber plus ? registers, the mc145220 may be cascaded with other peripherals featuring bitgrabber plus without requiring leading dummy bits or multiple address bits in the serial data stream. in addition, bitgrabber plus peripherals may be cascaded with existing bitgrabber ? peripherals. because this device is a dual synthesizer, a single steering bit is used in the serial data stream to direct the data to either side of the chip. the phase/frequency detectors have linear transfer functions (no dead zones). the current delivered by the current source/sink outputs is controllable via the serial port. also featured are lowpower standby for either one or both loops and onboard support of an external crystal. in addition, the part may be configured such that the ref in pin accepts an external reference signal. in this configuration, the ref out pin may be programmed to output the ref in frequency divided by 1, 2, 4, 8, or 16. ? operating frequency: 40 to 1100 mhz ? operating supply voltage range: 2.7 to 5.5 v ? supply current: both plls operating e 12 ma nominal one pll operating, one on standby e 6.5 ma nominal both plls on standby e 30 m a maximum ? phase detector output current: up to 2 ma @ 5 v up to 1 ma @ 3 v ? operating temperature range: 40 to 85 c ? independent r counters allow use of different step sizes for each loop ? doublebuffered r register e reference and loop divide ratios updated simultaneously ? r counter division range: 1 and 10 to 8,191 ? dualmodulus capability provides total division of the vco frequency up to 262,143 ? direct interface to motorola spi data port ? evaluation kit available (part number mc145220evk) ? see application note an1253/d for lowpass filter design, and an1277/d for offset reference plls for fine resolution or fast hopping bitgrabber and bitgrabber plus are trademarks of motorola, inc. order this document by mc145220/d semiconductor technical data pin assignment f suffix sog package case 803c dt suffix tssop case 948d ordering information MC145220F sog package mc145220dt tssop 20 1 20 1 gnd ld 13 14 15 16 clk d in pd out / f r 8 7 6 5 4 3 2 1 f in f in gnd pd out / f r ld ref out ref in 18 19 20 17 f in enb 11 12 10 9 output a v+ v+ rx / f v rx / f v f in ? motorola, inc. 1998 rev 4 1/98 tn98012300 archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 2 8 7 f in f in 2 1 3 buffer and control ref out ref in 23 7 13 bitgrabber plus r register 16 bits rs rs 13stage r counter 13stage r counter bitgrabber plus a register 23 bits a and n counters 32/33 or 64/65 prescaler ratio 18 32/33 or 64/65 prescaler a & n counters 23 bitgrabber plus a register 23 bits ratio 13 14 f in f in 23 24 1/2 stage shift register address logic and storage 11 20 enb d in 19 clk 2 5 pll / pll select from a register (internal) mux f r f r f v f v port 17 16 10 18 phase/ frequency detector pair 2 bitgrabber plus c register 7 bits ld rx / f v output a pd out / f r ld rx/ f v pd out / f r bitgrabber plus c register 7 bits phase/ frequency detector pair stby (internal) stby (internal) 2 4 5 data out pin 9 = v+ (positive power to the main pll, reference circuit, and a portion of the serial port) pin 6 = gnd (ground to the main pll, reference circuit, and a portion of the serial port) pin 12 = v+ (positive power to pll and a portion of the serial port) pin 15 = gnd (ground to pll and a portion of the serial port) 13 18 16 2 3 polarity gain pda/b select 2 unused 2 to mux for output a unused polarity gain pda/b select 2 unused 2 2 (internal) (internal) f r f r f v f v block diagram double buffer archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 3 maximum ratings* (voltages referenced to gnd, unless otherwise stated) symbol parameter value unit v+, v+ dc supply voltage 0.5 to + 6.0 v v in dc input voltage 0.5 to v+ + 0.5 v v out dc output voltage 0.5 to v+ + 0.5 v i in dc input current, per pin 10 ma i out dc output current, per pin 20 ma i dc supply current, v+, v+ , gnd, and gnd pins 30 ma p d power dissipation, per package 300 mw t stg storage temperature 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin descriptions section. electrical characteristics (v+ = v+ = 2.7 to 5.5 v, gnd = gnd , voltages referenced to gnd, t a = 40 to 85 c, unless otherwise stated) symbol parameter test condition guaranteed limit unit v il maximum lowlevel input voltage (d in , clk, enb , ref in ) device in reference mode, dc coupled 0.3 x v+ v v ih minimum highlevel input voltage (d in , clk, enb , ref in ) device in reference mode, dc coupled 0.7 x v+ v v hys minimum hysteresis voltage (clk, enb ) 100 mv v ol maximum lowlevel output voltage (ld, ld , ref out , output a) i out = 20 m a, device in reference mode; output a not selected as port 0.1 v v oh minimum highlevel output voltage (ref out , output a) i out = 20 m a, device in reference mode; output a not selected as port v+ 0.1 v i ol minimum lowlevel output current (ref out ) v out = 0.3 v 0.5 ma i ol minimum lowlevel output current (pd out / f r , pd out / f r , rx / f v , rx / f v ) v out = 0.3 v; phase/frequency detectors configured with f r , f v outputs 0.5 ma i ol minimum lowlevel output current (output a) v out = 0.3 v 0.5 ma i ol minimum lowlevel output current (ld, ld ) v out = 0.3 v 0.5 ma i oh minimum highlevel output current (ref out ) v out = v+ 0.3 v 0.4 ma i oh minimum highlevel output current (pd out / f r , pd out / f r , rx / f v , rx / f v ) v out = v+ 0.3 v; phase/frequency detectors configured with f r , f v outputs 0.4 ma i oh minimum highlevel output current (output a) v out = v+ 0.3 v; output a not selected as port 0.4 ma i in maximum input leakage current (d in , clk, enb , ref in ) v in = v+ or gnd; device in xtal mode 1.0 m a i in maximum input current (ref in ) v in = v+ or gnd; device in reference mode 150 m a i oz maximum output leakage current (pd out / f r , pd out / f r ) v out = v+ or gnd; phase/frequency detectors configured with pd out output, output in high impedance state 150 na i oz maximum output leakage current (output a, ld, ld ) v out = v+ or gnd; output a selected as port; output in highimpedance state 5 m a i stby maximum standby supply current v in = v+ or gnd; outputs open; both plls in standby mode, shutdown crystal mode or ref out staticlow reference mode 30 m a i t total operating supply current f in = f in = 1.1 ghz; both loops active; ref in = 13 mhz @ 1 v pp; output a = inactive; all outputs = no connect; d in , enb , clk = v+ or gnd; phase/frequency detectors configured with f r , f v outputs * ma * the nominal value is 12 ma. this is not a guaranteed limit. this device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. however, precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this highimpedance circuit. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 4 analog characteristics e current source/sink outputs e pd out / f r and pd out / f r (phase/frequency detectors configured with pd out outputs, i out 2 ma @v+ = v+ = 4.5 to 5.5 v, i out 1 ma @v+ = v+ = 2.7 to 4.4 v, gnd = gnd , voltages referenced to gnd) parameter test condition guaranteed limit unit maximum source current variation parttopart (notes 3 and 4) v out = 0.5 x v+ 20 % maximum sinkversussource mismatch (note 3) v out = 0.5 x v+ 12 % output voltage range (note 3) i out variation 20% 0.5 to v+ 0.5 v v notes: 1. percentages calculated using the following formula: (maximum value minimum value)/maximum value. 2. see rx pin description for external resistor values. 3. this parameter is guaranteed for a given temperature within 40 to 85 c and given supply voltage within 2.7 to 5.5 v. 4. applicable for the rx/ f v or rx / f v reference pin tied to the gnd or gnd pin through a resistor. see pin descriptions for suggested resistor values. ac interface characteristics (v+ = v+ = 2.7 to 5.5 v, gnd = gnd , t a = 40 to 85 c, c l = 25 pf, input t r = t f = 10 ns) symbol parameter guaranteed limit unit f clk serial data clk frequency (figure 1) note: refer to clock t w below dc to 2.0 mhz t plh , t phl maximum propagation delay, clk to output a (selected as data out) (figures 1 and 5) 200 ns t pzl , t plz maximum propagation delay, enb to output a (selected as port) (figures 2 and 6) 200 ns t tlh , t thl maximum output transition time, output a; t thl only, on output a when selected as port (figures 1, 5, and 6) 200 ns c in maximum input capacitance e d in , clk, enb 10 pf timing requirements (v+ = v+ = 2.7 to 5.5 v, gnd = gnd , t a = 40 to 85 c, input t r = t f = 10 ns unless otherwise indicated) symbol parameter guaranteed limit unit t su , t h minimum setup and hold times, d in versus clk (figure 3) 50 ns t su , t h , t rec minimum setup, hold, and recovery times, enb versus clk (figure 4) 100 ns t w minimum pulse width, enb (figure 4) * cycles t w minimum pulse width, clk (figure 1) 250 ns t r , t f maximum input rise and fall times e clk (figure 1) 100 m s * the minimum limit is 3 ref in cycles or 195 f in or f in cycles with selection of a 64/65 prescale ratio or 99 f in or f in cycles with selection of a 32/33 prescale ratio, whichever is greater. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 5 figure 1. figure 2. 10% v+ gnd 1/f clk output a (data out) clk 90% 50% 90% 50% 10% t plh t phl t tlh t thl t w t w t f t r enb output a 10% v+ gnd 50% t plz 50% t pzl d in clk 50% valid 50% t su t h v+ gnd v+ gnd figure 3. clk enb 50% t su t h first clock last clock t rec 50% v+ gnd v+ gnd t w t w figure 4. test point device under test c l * * includes all probe and fixture capacitance. test point device under test c l * * includes all probe and fixture capacitance. v+ 7.5 k w figure 5. figure 6. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 6 loop specifications (v+ = v+ = 2.7 to 5.5 v unless otherwise indicated, gnd = gnd , t a = 40 to 85 c) guaranteed operating range symbol parameter test condition min max unit p in input sensitivity range, f in or f in (figure 7) 40 mhz frequency < 300 mhz 300 mhz frequency < 700 mhz 700 mhz frequency < 1100 mhz 2 5 16 8 6 4 dbm* d p in difference allowed between f in and f in 10 db e isolation between f in and f in 15 db f ref input frequency, ref in externally driven in reference mode (figure 8) v in 400 mv pp, r counter set to divide ratio such that f r 1 mhz, ref counter set to divide ratio such that ref out 5 mhz 4 27 mhz f xtal crystal frequency, crystal mode (figure 9) c1 30 pf, c2 30 pf, includes stray capacitance; r counter and ref counter same as above v+ = 2.7 v v+ = 3.5 v v+ = 4.5 v v+ = 5.5 v 2 2 2 2 10 13 15 15 mhz f out output frequency, ref out (figures 10 and 12) c l = 25 pf dc 5 mhz f operating frequency of the phase detectors dc 1 mhz t w output pulse width, f r , f v, f r , f v (figures 11 and 12) f r in phase with f v , c l = 25 pf 16 125 ns c in input capacitance, ref in e 5 pf * power level at the input to the dc block. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 7 device under test test point f in output a figure 7. test circuit (f v ) figure 8. test circuit e reference mode dc block 50 w pad sine wave generator 50 w f in gnd v+ gnd v+ device under test test point ref in output a (f r ) 0.01 m f 50 w * sine wave generator 50 w gnd v+ gnd v+ v in test point ref out * characteristic impedance note: alternately, the 50 w pad may be a t network. device under test test point ref in output a figure 9. test circuit e crystal mode (f r ) ref out gnd v+ gnd v+ c1 c2 ref out 1/f out 50% figure 10. switching waveform output t w 50% figure 11. switching waveform test point device under test c l * * includes all probe and fixture capacitance. figure 12. test circuit archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 8 frequency (mhz) point impedance ( w ) 3 v supply 5 v supply 50 400 800 1100 e f g h 1900 + j 149 878 + j 703 705 + j 208 215 j 69.3 1930 + j 214 746 + j 741 626 + j 327 243 j 61.3 frequency (mhz) point impedance ( w ) 3 v supply 5 v supply 50 400 800 1100 a b c d 1900 j 157 1440 j 228 552 j 380 196 j 141 1970 j 102 1510 + j 19 671 j 334 223 j 147 f in (pin 8) sog package f in (pin 13) sog package figure 13. nominal input impedance of f in and f in e series format (r + jx) (50 1100 mhz) j2 j1 a b c d f in (pin 8) sog package j2 j1 e f g h f in (pin 13) sog package archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 9 pin descriptions digital interface pins d in serial data input (pin 20) the bit stream begins with the msb and is shifted in on the lowtohigh transition of clk. the bit pattern is 1 byte (8 bits) long to access the c or configuration registers, 2 bytes (16 bits) to access the first buffer of the r registers, or 3 bytes (24 bits) to access the a registers (see table 1). the values in the registers do not change during shifting because the transfer of data to the registers is controlled by enb . note the value programmed for the n counter must be greater than or equal to the value of the a counter. the 13 lsbs of the r registers are doublebuffered. as in- dicated above, data is latched into the first buffer on a 16bit transfer. (the 3 msbs are not doublebuffered and have an immediate effect after a 16bit transfer.) the two second buffers of the r register contain the two 13bit divide ratios for the r counters. these second buffers are loaded with the contents of the first buffer as follows. whenever the a regis- ter is loaded, the rs (second) buffer is loaded from the r (first) buffer. similarly, whenever the a register is loaded, the rs (second) buffer is updated from the r (first) buffer. this allows presenting new values to the r, a, and n counters simultaneously. note that two different r counter divide ratios may be established: one for the main pll and another for pll . the bit stream does not need address bits due to the inno- vative bitgrabber plus registers. a steering bit is used to direct data to either the main pll or pll section of the chip. data is retained in the registers over a supply range of 2.7 to 5.5 v. the formats are shown in figures 14, 15, and 16. d in typically switches near 50% of v+ to maximize noise immunity. this input can be directly interfaced to cmos devices with outputs guaranteed to switch near railtorail. when interfacing to nmos or ttl devices, either a level shifter (mc74hc14a, mc14504b) or pullup resistor of 1 k w to 10 k w must be used. parameters to consider when sizing the resistor are worstcase i ol of the driving device, maxi- mum tolerable power consumption, and maximum data rate. table 1. register access (msbs are shifted in first; c0, r0, and a0 are the lsbs) number of clocks accessed register bit nomenclature 8 16 24 other values 32 values > 32 c registers r register, first buffer a registers not allowed see figures 24 to 27 c7, c6, c5, . . ., c0 r15, r14, r13, . . ., r0 a23, a22, a21, . . ., a0 clk serial data clock input (pin 19) lowtohigh transitions on clk shift bits available at the d in pin, while hightolow transitions shift bits from output a (when configured as data out, see pin 10). the 241/2 stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. eight clock cycles are required to access the c registers. sixteen clock cycles are needed for the first buffer of the r register. twentyfour cycles are used to access the a regis- ters. see table 1 and figures 14, 15, and 16. the number of clocks required for cascaded devices is shown in figures 25 through 27. clk typically switches near 50% of v+ and has a schmitt triggered input buffer. slow clk rise and fall times are al- lowed. see the last paragraph of d in for more information. note to guarantee proper operation of the poweron reset (por) circuit, the clk pin must be held at gnd (with enb being a don't care) or enb must be held at the potential of the v+ pin (with clk be- ing a don't care) during powerup. floating, tog- gling, or having these pins in the wrong state during powerup does not harm the chip, but causes two potentially undesirable effects. first, the outputs of the device power up in an unknown state. second, if two devices are cascaded, the a registers must be written twice after power up. after these two accesses, the two cascaded chips perform normally. enb activelow enable input (pin 11) this pin is used to activate the serial interface to allow the transfer of data to/from the device. when enb is in an inac- tive high state, shifting is inhibited and the port is held in the initialized state. to transfer data to the device, enb (which must start inactive high) is taken low, a serial transfer is made via d in and clk, and enb is taken back high. the lowtohigh transition on enb transfers data to the c or a registers and first buffer of the r register, depending on the data stream length per table 1. note transitions on enb must not be attempted while clk is high. this puts the device out of synchro- nization with the microcontroller. resynchro- nization occurs whenever enb is high and clk is low. this input is schmitttriggered and switches near 50% of v+, thereby minimizing the chance of loading erroneous data into the registers. see the last paragraph of d in for more information. for por information, see the note for the clk pin . archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 10 output a configurable digital output (pin 10) output a is selectable as f r , f v , f r , f v , data out, or port. bits a21 and a22 and the steering bit (a23) control the selec- tion; see figure 15. when selected as port, the pin becomes an opendrain nchannel mosfet output. as such, a pullup device is needed for pin 10. with all other selections, the pin is a totempole (pushpull) output. if a22 = a21 = high, output a is configured as f r when the steering bit is low and f r when the bit is high. these signals are the buffered outputs of the 13stage r counters. the sig- nals appear as normally low and pulse high. the signals can be used to verify the divide ratios of the r counters. these ratios extend from 10 to 8191 and are determined by the binary value loaded into bits r0 r12 in the r register. also, direct access to the phase detectors via the ref in pin is allowed by choosing a divide value of one. see figure 16. the maximum frequency at which the phase detectors oper- ate is 1 mhz. therefore, the frequency of f r and f r should not exceed 1 mhz. if a22 = high and a21 = low, output a is configured as f v when the steering bit is low and f v when the bit is high. these signals are the buffered outputs of the 12stage n counters. the signals appear as normally low and pulse high. the signals can be used to verify the operation of the prescalers, a counters, and n counters. the divide ratio be- tween the f in or f in input and the f v or f v signal is n x p + a. n is the divide ratio of the n counter, p is 32 with a 32/33 prescale ratio or 64 with a 64/65 prescale ratio, and a is the divide ratio of the a counter. these ratios are determined by bits loaded into the a registers. see figure 15. the maxi- mum frequency at which the phase detectors operate is 1 mhz. therefore, the frequency of f v and f v should not exceed 1 mhz. if a22 = low and a21 = high, output a is configured as data out. this signal is the serial output of the 241/2 stage shift register. the bit stream is shifted out on the hightolow transition of the clk input. upon power up, output a is automatically configured as data out to facilitate cascading devices. if a22 = a21 = low, output a is configured as port. this signal is a generalpurpose digital output which may be used as an mcu port expander. this signal is low when the port bit (c1) of the c register is low, and high impedance when the port bit is high. see figure 14. reference pins ref in and ref out reference oscillator input and output (pins 1 and 2) configurable pins for a crystal or an external reference. this pair of pins can be configured in one of two modes: the crystal mode or the reference mode. bits r13, r14, and r15 in the r register control the modes as shown in figure 16. in the crystal mode, these pins form a reference oscillator when connected to terminals of an external parallelreso- nant crystal. frequencysetting capacitors of appropriate values, as recommended by the crystal supplier, are con- nected from each of the two pins to ground (up to a maximum of 30 pf each, including stray capacitance). an external re- sistor of 1 m w to 15 m w is connected directly across the pins to ensure linear operation of the amplifier. the required con- nections for the crystal are shown in figure 9. to turn on the oscillator, bits r15, r14, and r13 must have an octal value of one (001 in binary). this is the activecrystal mode shown in figure 16. in this mode, the crystal oscillator runs and the r counter divides the crystal frequency, unless the part is in standby. if the part is placed in standby via the c or c regis- ter, the oscillator runs, but the r or r counter is stopped, re- spectively. however, if bits r15 to r13 have a value of 0, the oscillator is stopped, which saves additional power. this is the shutdown crystal mode shown in figure 16, and can be engaged whether in standby or not. in the reference mode, ref in (pin 1) accepts a signal from an external reference oscillator, such as a tcxo. a signal swinging from at least the v il to v ih levels listed in the elec- trical characteristics table may be directly coupled to the pin. if the signal is less than this level, ac coupling must be used as shown in figure 8. the accoupled signal must be at least 400 mv pp. due to an onboard resistor which is engaged in the reference modes, an external biasing resistor tied between ref in and ref out is not required. with the reference mode, the ref out pin is configured as the output of a divider. as an example, if bits r15, r14, and r13 have an octal value of seven, the frequency at ref out is the ref in frequency divided by 16. in addition, figure 16 shows how to obtain ratios of eight, four, and two. a ratio of onetoone can be obtained with an octal value of three. upon power up, a ratio of eight is automatically in- itialized. the maximum frequency capability of the ref out pin is 5 mhz for large output swings (v oh to v ol ) and 25 pf loads. therefore, for ref in frequencies above 5 mhz, the onetoone ratio may not be used for these large signal swing and large c l requirements. likewise, for ref in fre- quencies above 10 mhz, the ratio must be more than two. if ref out is unused, an octal value of two should be used for r15, r14, and r13 and the ref out pin should be floated. a value of two allows ref in to be functional while disabling ref out , which minimizes dynamic power con- sumption and electromagnetic interference (emi). loop pins f in , f in and f in , f in frequency inputs (pins 8, 7 and 13, 14) these pins feed the onboard rf amplifiers which drive the prescalers. these inputs may be fed differentially. however, they usually are used in singleended configurations (shown in figure 7). note that f in is driven while f in must be tied to ac ground (via capacitor). the signal sources driving these pins originate from external vcos. motorola does not recommend driving f in while terminating f in because this configuration is not tested for sensitivity. the sensitivity is dependent on the frequency as shown in the loop specifications table. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 11 pd out / f r , pd out / f r singleended phase/frequency detector outputs (pins 4 and 17) when the c2 bits in the c or c registers are low, these pins are independently configured as singleended outputs pd out or pd out , respectively. as such, each pin is a three state currentsource/sink output for use as a loop error sig- nal when combined with an external lowpass filter. the phase/frequency detector is characterized by a linear trans- fer function. the operation of the phase/frequency detector is described below and is shown in figure 17. pol bit (c0) in the c register = low (see figure 14) frequency of f v > f r or phase of f v leading f r : current sinking pulses from a floating state frequency of f v < f r or phase of f v lagging f r : current sourcing pulses from a floating state frequency and phase of f v = f r : essentially a floating state; voltage at pin determined by loop filter pol bit (c0) = high frequency of f v > f r or phase of f v leading f r : current sourcing pulses from a floating state frequency of f v < f r or phase of f v lagging f r : current sinking pulses from a floating state frequency and phase of f v = f r : essentially a floating state; voltage at pin determined by loop filter these outputs can be enabled, disabled, and inverted via the c and c registers. if desired, these pins can be forced to the floating state by utilization of the standby feature in the c or c registers (bit c6). this is a patented feature. the phase detector gain is controllable by bits c4 and c5: gain (in amps per radian) = pd out current in amps divided by 2 p . pd out / f r , rx/ f v and pd out / f r , rx / f v doubleended phase/frequency detector outputs (pins 4, 5 and 17, 16) when the c2 bits in the c or c registers are high, these two pairs of pins are independently configured as double ended outputs f r , f v or f r , f v , respectively. as such, these outputs can be combined externally to generate a loop error signal. through use of a motorola patented technique, the detector's dead zone has been eliminated. therefore, the phase/frequency detector is characterized by a linear trans- fer function. the operation of the phase/frequency detectors are described below and are shown in figure 17. pol bit (c0) in the c register = low (see figure 14) frequency of f v > f r or phase of f v leading f r : f v = negative pulses, f r = essentially high frequency of f v < f r or phase of f v lagging f r : f v = essentially high, f r = negative pulses frequency and phase of f v = f r : f v and f r remain essentially high, except for a small minimum time period when both pulse low in phase pol bit (c0) = high frequency of f v > f r or phase of f v leading f r : f r = negative pulses, f v = essentially high frequency of f v < f r or phase of f v lagging f r : f r = essentially high, f v = negative pulses frequency and phase of f v = f r : f v and f r remain essentially high, except for a small minimum time period when both pulse low in phase these outputs can be enabled, disabled, or interchanged via c register bits c6 or c0. this is a patented feature. note that when disabled in standby, these outputs are forced to their rest condition (high state). see figure 14. the f r and f v output signals swing from approximately gnd to v+. ld and ld lock detector outputs (pins 3 and 18) each output is essentially at a highimpedance state with very narrow lowgoing pulses of a few nanoseconds when the respective loop is locked (f r and f v of the same phase and frequency). the output pulses low when f v and f r are out of phase or different frequencies. ld is the logical and- ing of f r and f v , while ld is the logical anding of f r and f v . see figure 17. upon power up, onchip initialization circuitry forces ld and ld to the highimpedance state. these pins are low during standby. if unused, ld should be tied to gnd and ld should be tied to gnd . these outputs have opendrain nchannel mosfet driv- ers. this facilitates a wiredor function. see figure 21. rx/ f v and rx / f v external current setting resistors (pins 5 and 16) when the c2 bits in the c or c registers are low, these two pins are independently configured as current setting pins rx or rx , respectively. as such, resistors tied between each of these pins and gnd and gnd , in conjunction with bits c4 and c5 in the c and c registers, determine the amount of current that the pd out pins sink and source. when bits c4 and c5 are both set high, the maximum current is obtained; see table 2 for other values of current. table 2. pd out or pd out current c5 c4 current 0 0 1 1 0 1 0 1 5% 50% 80% 100% the formula for determining the value of rx or rx is as follows. rx = v1 v2 i where rx is the value of external resistor in ohms, v1 is the supply voltage, v2 is 1.5 v for a reference current through rx of 100 m a or 1.745 v for a reference current of 200 m a, and i is the reference current flowing through rx or rx . the reference current flowing through rx or rx is multi- plied by a factor of approximately 10 (in the 100% current mode) and delivered by the pd out or pd out pin, respectively. to achieve a maximum phase detector output current of 1 ma, the resistor should be about 15 k w when a 3 v supply is employed. see table 3. table 3. rx values supply voltage rx pd out or pd out current in 100% mode 3 v 5 v 15 k w 16 k w 1 ma 2 ma archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 12 do not use a decoupling capacitor on the rx or rx pin. use of a capacitor causes undesirable current spikes to ap- pear on the phase detector output when invoking the standby mode. power supply pins v+ and v+ positive supply potentials (pins 9 and 12) v+ supplies power to the main pll, reference circuit, and a portion of the serial port. v+ supplies power to pll and a portion of the serial port. both v+ and v+ must be at the same voltage level and may range from 2.7 v to 5.5 v with respect to the gnd and gnd pins. for optimum performance, v+ should be bypassed to gnd and v+ bypassed to gnd using separate lowinduc- tance capacitors mounted very close to the mc145220. lead lengths and printed circuit board traces to the capacitors should be minimized. (the very fast switching speed of the device can cause excessive current spikes on the power leads if they are improperly bypassed.) gnd and gnd grounds (pins 6 and 15) the gnd pin is the ground for the main pll and gnd is the ground for pll . archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 13 enb clk * d in c7 c6 c5 c4 c3 c2 c1 c0 12345678 msb lsb * at this point, the new byte is transferred to the c or c register and stored. no other registers are affected. c7 steer: used to direct the data to either the c or c register. a low level directs data to the c register; a high level is for the c register. c6 standby: when set high, places both the main pll and pll (when c6 is set in the c register) or pll only (when c6 is set in the c register) in the standby mode for reduced power consumption. the associated pd out is forced to the floating state, the associated counters (a, n, and r) are inhibited from counting, the associated rx current is shut off, and the associated prescaler stops counting and is placed in a low current mode. the associated doubleended phase/frequency detector outputs are forced to a high level. in standby, the associated ld output is placed in the lowstate, thus indicating anot lockedo (open loop). during standby, data is retained in all registers and any register may be accessed. in standby, the condition of the ref/osc circuitry is determined by bits r13, r14, and r15 in the r register per figure 16. however, if ref out = static low is selected, the internal feedback resistor is disconnected and the ref in is inhibited when both pll and pll are placed in standby via the c register. thus, the ref in only presents a capacitive load. note : pll/pll standby does not affect the other modes of the ref/osc circuitry as determined by bits r13, r14, and r15 in the r register. the pll standby mode (controlled from the c register) has no effect on the ref/osc circuit. when c6 is reset low, the associated pll (or plls) is (are) taken out of standby in two steps. first, the ref in (only in 1 mode, pll/pll in standby) resistor is reconnected, ref in (only 1 mode) is gated on, all counters are enabled, and the rx current is enabled. any f r and f v signals are inhibited from toggling the phase/frequency detectors and lock detectors. second, when the appropriate f r pulse occurs, the a and n counters are jam loaded, the prescaler is gated on, and the phase/frequency and lock detectors are initialized. immediately after the jam load, the a, n, and r counters begin counting down together. at this point, the f r and f v pulses are enabled to the phase and lock detectors. (patented feature.) c5, c4 i2, i1: independently controls the pd out or pd out source/sink current per table 2. with both bits high, the maximum current (as set by rx or rx ) is available. por forces c5 and c4 to high levels. c3 spare: unused c2 pda/b: independently selects which phase/frequency detector is to be used. when set high, the doubleended detector is selected with outputs f r and f v or f r and f v . when reset low, the current source/sink detector is selected with outputs pd out or pd out . in the second case, the appropriate rx or rx pin is tied to an external resistor. por forces c2 low. c1 port: when the output a pin is selected as aporto via bits a22 and a21, c1 of the c register determines the state of output a. when c1 is set high, output a is forced to the highimpedance state; c1 low forces output a low. the port bit is not affected by the standby mode. note : c1 of the c register is not used in any mode. c0 pol: selects the output polarity of the associated phase/frequency detectors. when set high, this bit inverts the associated current source/sink output and interchanges the associated doubleended output relative to the waveforms in figure 17. also, see the phase detector output pin descriptions for more information. this bit is cleared low at power up. figure 14. c and c register accesses and format (8 clock cycles are used) archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 14 ??? ??? ??? a22 ??? a21 ??? a20 ??? a19 ??? a18 ??? ??? a17 ??? a16 ??? ??? a15 ??? a14 ??? ??? a13 ??? a12 ??? a11 ??? a10 ??? a9 ??? ??? a8 ??? a7 ??? ??? a6 ??? a5 ??? ??? a4 ??? a3 ??? a2 ??? a1 ??? ??? ??? a0 ??? ??? ??? ??? a23 note 3 23456789 1011121314151 617181920212 22324 1 msb lsb 0 0 1 1 0 1 0 1 port data out f f binary value output a function (notes 1 and 4) 0 0 0 0 3 0 1 2 3 e a counter = 0 a counter = 1 a counter = 2 a counter = 3 a counter = 62 4 1 not allowed hexadecimal value for a counter 3 4 f 0 a counter = 63 not allowed . . . f . . . f not allowed . . . . . . notes: 1. a power-on initialize circuit forces the output a function to default to data out. 2. the values programmed for the n counter must be greater than or equal to the values programmed for the a counter. this results in a total divide value = n x p + a where 3. at this point, the three new bytes are transferred to the a register if bit a23 is a a0o or a register if a23 is a a1o. in addition, the 13 lsbs in the first buf fer of the r register are enb clk figure 15. a and a a register accesses and format (24 clock cycles are used) d in 0 1 32/33 64/65 prescale ratio 0 1 main pll, a register pll , a register steer n is the value programmed for the n counter, p is 32 if bit a20 is low or 64 if a20 is high, and a is the value programmed for the a counter. aa 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 2 0 1 2 3 not allowed not allowed not allowed not allowed not allowed . . . f f . . . f f . . . e f n counter = 4094 n counter = 4095 hexadecimal value for n counter 014 . . . . . . . . . n counter = 19 n counter = 18 n counter = 20 (note 4) and bits a7 and a6 r v or f or f r v a a transferred to the r register's relative second buffer , rs or rs . thus, the r, n, and a (or r , n , and a ) counters can be presented new divide ratios at the same time. the first buffer of the r register is not affected. the c or c registers are not af fected. a a a a aa 4. a a0o for the steering bit allows selection of f , f , data out, or port by bits a21 and a22. a a1o for the steering bit allows selection of f , , f , data out, or port. r a rv v a archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 15 enb clk d in 123 45 78 msb lsb 910 11 12 13 14 15 16 0 0 0 0 0 0 0 0 0 0 0 0 0 f f 0 0 0 0 0 0 0 0 0 0 0 0 0 f f 0 1 2 3 4 5 6 7 8 9 a b c e f not allowed r counter = 1 (note 6) not allowed not allowed not allowed not allowed not allowed not allowed not allowed not allowed r counter = 10 r counter = 11 r counter = 12 r counter = 8190 r counter = 8191 hexadecimal value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 binary value 0 1 2 3 4 5 6 7 crystal mode, shut down crystal mode, active reference mode, ref in enabled and ref out static low reference mode, ref out = ref in (buffered) reference mode, ref out = ref in /2 reference mode, ref out = ref in /4 reference mode, ref out = ref in / 8 (note 3) reference mode, ref out = ref in /16 octal value notes: 1. bits r15 r13 control the configurable abuffer and controlo block (see block diagram). 2. bits r12 r0 control the a13stage r countero blocks (see block diagram). 3. a poweron initialize circuit forces a default ref in to ref out ratio of eight. 4. at this point, bits r13, r14, and r15 are stored and sent to the abuffer and controlo block in the block diagram. bits r0 r12 are loaded into the first buffer in the doublebuffered section of the r register. therefore, the r or r counter divide ratio is not altered yet and retains the previous ratio loaded. the c, c a , a, and a a registers are not affected. 5. bits r0 r12 are transferred to the second buffer of the r register (rs in the block diagram) on a subsequent 24bit write to the a register. the bits are transferred to rs a on a subsequent 24bit write to the a a register. the respective r counter begins dividing by the new ratio after completing the rest of its present count cycle. 6. allows direct access to reference input of phase/frequency detectors. note 4 6 r1 r0r5 r4 r3 r2 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 figure 16. r register access and format (16 clock cycles are used) archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 16 notes: 1. at this point, when both f r and f v are in phase, the output source and sink circuits are turned on for a short interval. 2. the pd out either sources or sinks current during outoflock conditions. when locked in phase and frequency, the output is mostly in a floating condition and the voltage at that pin is determined by the lowpass filter capacitor. pd out , f r , and f v are shown with the polarity bit (pol) = low; see figure 14 for pol. 3. v h = high voltage level, v l = low voltage level. 4. the waveforms are applicable to both the main pll and pll . f r reference ref in r f v feedback f in (n x p + a) pd out f r f v ld v h v l sourcing current high impedance v h v l float v h v l v l v l v h sinking current note 1 figure 17. phase/frequency detectors and lock detector output waveforms archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 17 design considerations crystal oscillator considerations the following options may be considered to provide a ref- erence frequency to motorola's cmos frequency synthe- sizers. use of a hybrid crystal oscillator commercially available temperaturecompensated crystal oscillators (tcxos) or crystalcontrolled data clock oscilla- tors provide very stable reference frequencies. an oscillator capable of cmos logic levels at the output may be direct or dc coupled to ref in . if the oscillator does not have cmos logic levels on the outputs, capacitive or ac coupling to ref in must be used. see figure 8. for additional information about tcxos and data clock oscillators, please consult the latest version of the eem elec- tronic engineers master catalog, the gold book, or similar publications. design an offchip reference the user may design an offchip crystal oscillator using discrete transistors or ics specifically developed for crystal oscillator applications, such as the mc12061 mecl device. the reference signal from the mecl device is ac coupled to ref in . (see figure 8.) for large amplitude signals (standard cmos logic levels), dc coupling may be used. use of the onchip oscillator circuitry the onchip amplifier (a digital inverter) along with an ap- propriate crystal may be used to provide a reference source frequency. a fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in figure 18. the crystal should be specified for a loading capacitance, c l , which does not exceed approximately 20 pf when used near the highest operating frequency of the mc145220. assuming r1 = 0 w , the shunt load capacitance, c l , pres- ented across the crystal can be estimated to be: c l = c in c out c in + c out + c a + c stray + c1 ? c2 c1 + c2 where c in = 5 pf (see figure 19) c out = 6 pf (see figure 19) c a = 1 pf (see figure 19) c1 and c2 = external capacitors (see figure 18) c stray = the total equivalent external circuit stray capacitance appearing across the crystal terminals the oscillator can be atrimmedo onfrequency by making either a portion or all of c1 variable. the crystal and associ- ated components must be located as close as possible to the ref in and ref out pins to minimize distortion, stray ca- pacitance, stray inductance, and startup stabilization time. circuit stray capacitance can also be handled by adding the appropriate stray value to the values for c in and c out . for this approach, the term c stray becomes zero in the above expression for c l . power is dissipated in the effective series resistance of the crystal, r e , in figure 20. the maximum drive level specified by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shift in operating frequency. r1 in figure 18 limits the drive level. the use of r1 is not necessary in most cases. to verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output fre- quency (f r ) at output a as a function of supply voltage. (ref out is not used because loading impacts the oscillator.) the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal decreases in fre- quency or becomes unstable with an increase in supply volt- age. the operating supply voltage must be reduced or r1 must be increased in value if the overdriven condition exists. note that the oscillator startup time is proportional to the value of r1. through the process of supplying crystals for use with cmos inverters, many crystal manufacturers have devel- oped expertise in cmos oscillator design with crystals. dis- cussions with such manufacturers can prove very helpful. see table 4. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 18 figure 18. pierce crystal oscillator circuit r1* c2c1 frequency synthesizer ref out ref in r f * may be needed in certain cases. see text. figure 19. parasitic capacitances of the amplifier and c stray c in c out ca ref in ref out c stray figure 20. equivalent crystal networks note: values are supplied by crystal manufacturer (parallel resonant crystal). 2 1 2 12 1 r s l s c s r e x e c o recommended reading technical note tn24, statek corp. technical note tn7, statek corp. e. hafner, athe piezoelectric crystal unit definitions and method of measuremento, proc. ieee, vol. 57, no. 2, feb. 1969. d. kemper, l. rosine, aquartz crystals for frequency controlo, electrot echnology , june 1969. p. j. ottowitz, aa guide to crystal selectiono, electronic design , may 1966. d. babin, adesigning crystal oscillatorso, machine design , march 7, 1985. d. babin, aguidelines for crystal oscillator designo, machine design , april 25, 1985. table 4. partial list of crystal manufacturers united states crystal corp. crystek crystal statek corp. fox electronics note: motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal man- ufacturers. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 19 assuming gain a is very large, then: z(s) = z = w n = phaselocked loop e lowpass filter design (b) a c r 2 c vco (a) f r f v r 1 r 1 r 2 k f k vco nc r 2 sc k f k vco ncr 1 w n r 2 c 2 r 2 sc + 1 r 1 sc note: for (b), r 1 is frequently split into two series resistors; each resistor is equal to r 1 divided by 2. a capacitor c c is then placed from the midpoint to ground to further filter the error pulses. the value of c c should be such that the corner frequency of this network does not significantly affect w n . definitions: n = total division ratio in feedback loop k f (phase detector gain) = i pdout /2 p amps per radian for pd out k f (phase detector gain) = v+/2 p volts per radian for f v and f r k vco (vco transfer function) = 2 pd f vco d v vco for a nominal design starting point, the user might consider a damping factor z 0.7 and a natural loop frequency w n (2 p f r /50) where f r is the frequency at the phase detector input. larger w n values result in faster loop lock times and, for similar sideband filtering, higher f r related vco sidebands. recommended reading: gardner, floyd m., phaselock t echniques (second edition). new york, wileyinterscience, 1979. manassewitsch, vadim, frequency synthesizers: theory and design (second edition). new york, wileyinterscience, 1980. blanchard, alain, phaselocked loops: application to coherent receiver design. new york, wileyinterscience, 1976. egan, william f., frequency synthesis by phase lock. new york, wileyinterscience, 1981. rohde, ulrich l., digital pll frequency synthesizers theory and design. englewood cliffs, nj, prenticehall, 1983. berlin, howard m., design of phaselocked loop circuits, with experiments. indianapolis, howard w. sams and co., 1978. kinley, harold, the pll synthesizer cookbook. blue ridge summit, pa, tab books, 1980. seidman, arthur h., integrated circuits applications handbook , chapter 17, pp. 538586. new york, john wiley & sons. fadrhons, jan, adesign and analyze plls on a programmable calculator,o edn . march 5, 1980. an535, phaselocked loop design fundamentals, motorola semiconductor products, inc., 1970. ar254, phaselocked loop design articles, motorola semiconductor products, inc., reprinted with permission from electronic design, 1987. an1253, an improved pll design method without w n and z , motorola semiconductor products, inc., 1995. + k vco c n k f 1 + src note: for (a), using k f in amps per radian with the filter's impedance transfer function, z(s), maintains units of volts per radian for the detector/ filter combination. additional sideband filtering can be accomplished by adding a capacitor c across r. the corner w c = 1/rc should be chosen such that w n is not significantly affected. c vco r pd out radians per volt either loop filter (a) or (b) is frequently followed by additional sideband filtering to further attenuate f r related vco sidebands. this additional filtering may be active or passive. = w n rc 2 z(s) = z = w n = archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 20 20 19 18 17 16 15 14 13 12 11 lowpass filter vco output buffer +v +v 1 2 3 4 lowpass filter vco output 5 6 7 +v 9 8 10 +v mcu note 4 general purpose digital output ref in ref out ld pd out / f r rx / f v gnd f in f in v+ output a (port) d in clk ld pd out / f r rx / f v gnd f in f in v+ enb buffer mc145220 note 5 r1 q1 note 6 notes: 1. the pd out output is fed to an external loop filter. see the phaselocked loop e lowpass filter design page for additional informa- tion. 2. for optimum performance, bypass the v+ and v+ pins to gnd and gnd with lowinductance capacitors. 3. the r counter is programmed for a divide value = ref in /f r . typically, f r is the tuning resolution required for the vco. also, the vco frequency divided by f r = n t = n p + a; this determines the values (n, a) that must be programmed into the n and a counters, respectively. p is the lower divide ratio of the dualmodulus prescaler (i.e., 32 or 64). 4. pullup voltage must be at the same potential as the v+ pin or less. pullup device other than a resistor may be used. (pullup device not required when output a is configured as f r , f r , f v , f v , data out.) 5. ld and ld are opendrain outputs. this allows the wiredor configuration shown. note that r1 and q1 form the apullup deviceo. 6. use of q1 is optional and depends on loading. figure 21. application showing use of the two singleended phase/frequency detectors archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 21 20 19 18 17 16 15 14 13 12 11 lowpass filter vco output buffer +v +v 1 2 3 4 lowpass filter vco output 5 6 7 +v 9 8 10 +v mcu note 4 general purpose digital output ref in ref out ld pd out / f r rx / f v gnd f in f in v+ output a (port) d in clk ld pd out / f r rx / f v gnd f in f in v+ enb buffer mc145220 note 5 r1 q1 note 6 notes: 1. the f r and f v outputs are fed to an external combiner/loop filter. see the phaselocked loop e lowpass filter design page for additional information. the f r and f v outputs swing railtorail. therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter. 2. for optimum performance, bypass the v+ and v+ pins to gnd and gnd with lowinductance capacitors. 3. the r counter is programmed for a divide value = ref in /f r . typically, f r is the tuning resolution required for the vco. also, the vco frequency divided by f r = n t = n p + a; this determines the values (n, a) that must be programmed into the n and a counters, respectively. p is the lower divide ratio of the dualmodulus prescaler (i.e., 32 or 64). 4. pullup voltage must be at the same potential as the v+ pin or less. pullup device other than a resistor may be used. (pullup device not required when output a is configured as f r , f r , f v , f v , data out.) 5. ld and ld are opendrain outputs. this allows the wiredor configuration shown. note that r1 and q1 form the apullup deviceo. 6. use of q1 is optional and depends on loading. figure 22. application showing use of the two doubleended phase/frequency detectors archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 22 20 19 18 17 16 15 14 13 12 11 lowpass filter vco output buffer +v +v 1 2 3 4 lowpass filter vco output 5 6 7 +v 9 8 10 +v mcu note 4 general purpose digital output ref in ref out ld pd out / f r rx / f v gnd f in f in v+ output a (port) d in clk ld pd out / f r rx / f v gnd f in f in v+ enb buffer mc145220 note 5 r1 q1 note 6 notes: 1. see the phaselocked loop e lowpass filter design page for additional information. 2. for optimum performance, bypass the v+ and v+ pins to gnd and gnd with lowinductance capacitors. 3. the r counter is programmed for a divide value = ref in /f r . typically, f r is the tuning resolution required for the vco. also, the vco frequency divided by f r = n t = n p + a; this determines the values (n, a) that must be programmed into the n and a counters, respectively. p is the lower divide ratio of the dualmodulus prescaler (i.e., 32 or 64). 4. pullup voltage must be at the same potential as the v+ pin or less. pullup device other than a resistor may be used. (pullup device not required when output a is configured as f r , f r , f v , f v , data out.) 5. ld and ld are opendrain outputs. this allows the wiredor configuration shown. note that r1 and q1 form the apullup deviceo. 6. use of q1 is optional and depends on loading. figure 23. application showing use of both the single and doubleended phase/frequency detectors cmos mcu output a (data out) enb clkd in device #1 output a (data out) enb clkd in device #2 optional figure 24. cascading two devices note: see related figures 25, 26, and 27. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 23 1 2 7 8 9 10 15161718 232 425 26 3132 c or c register bits of device #2 in figure 24 *at this point, the new bytes are transferred to the c or c registers of both devices and stored. no other registers are af fected. c7 c6 c0 x x x x x x c7 c6 c0 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? clk ??? ??? ??? ??? ??? ??? * enb d in c or c register bits of device #1 in figure 24 figure 25. accessing the c or c registers of two cascaded mc145220 devices (32 clock cycles are used) archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 24 figure 26. accessing the a or a registers of two cascaded mc145220 devices (48 clock cycles are used) 12 7 8 9 151617 232425 3132 a or a register bits of device #1 in figure 24 a23 a22 a16 a15 a8 a7 a0 a23 a16 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 38 39 40 47 48 a9 a8 a0 ??? ??? ??? ??? ??? ??? *at this point, the new bytes are transferred to the a or a registers of both devices and stored. additionally, for both devices, the 13 lsbs in each of the first buf fers of the * clk enb d in a or a register bits of device #2 in figure 24 r registers are transferred to the respective r register 's second buffer. thus, the r, n, and a (r , n , and a ) counters can be presented new divide ratios at the same time. the first buffer of each r register is not affected. none of the c or c registers are af fected. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 25 12 7 8 9 151617 232425 r register bits of device #2 in figure 24 r register bits of device #1 in figure 24 r15 r14 r8 r7 r0 x x r15 ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? 31 32 33 39 40 r8 r7 r0 ??? ??? ??? ??? ??? note 1 notes applicable to each device: 1. at this point, bits r13, r14, and r15 are stored and sent to the buf fer and control block in the block diagram. bits r0 through r12 are loaded into the 2. see note of figure 26 for the method of loading the second buf fers in the r register to achieve new divide ratios. clk enb d in figure 27. accessing the r registers of two cascaded mc145220 devices (40 clock cycles are used) first buffer in the doublebuffered section of the r register . therefore, the r and r counter divide ratios are not altered yet and retain the previous ratios loaded. the other registers are not affected. archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 26 package dimensions f suffix sog (small outline gullwing) package case 803c01 dim a min max min max inches 12.35 12.80 0.486 0.504 millimeters b 5.10 5.45 0.201 0.215 c 1.95 2.05 0.077 0.081 d 0.35 0.50 0.014 0.020 e 0.81 0.032 f 12.40* 0.488* g 1.15 1.39 0.045 0.055 h 0.59 0.81 0.023 0.032 j 0.18 0.27 0.007 0.011 k 1.10 1.50 0.043 0.059 l 0.05 0.20 0.001 0.008 m 0 10 n 0.50 0.85 0.020 0.033 s 7.40 8.20 0.291 0.323 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.008) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.006) total in excess of the d dimension at maximum material condition. *approximate a 0.13 (0.005) m tb ss 0.13 (0.005) m b m s 10 pl g d 20 pl l c 0.10 (0.004) seating plane k n j m e 1 20 11 10 a f b t dt suffix tssop (thin shrunk small outline package) case 948d03 a t m b l d c g h j -u- 0.200 (0.008) dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 0.95 1.05 0.037 0.041 d 0.05 0.25 0.002 0.010 f 0.45 0.55 0.018 0.022 g 0.65 bsc 0.026 bsc h 0.275 0.375 0.010 0.015 j 0.09 0.24 0.004 0.009 k 0.16 0.32 0.006 0.013 l 6.30 6.50 0.248 0.256 m 0 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -u-. f m k k1 j j1 a a j1 0.09 0.18 0.004 0.007 k1 0.16 0.26 0.006 0.010 20 11 10 1 20 x k ref pin one identification seating plane -t- 0.100 (0.004) section a-a archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc145220 motorola wireless semiconductor solutions device data 27 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : motorola japan ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 13036752140 or 18004412447 4321 nishigotanda, shinagawaku, tokyo, japan. 81354878488 customer focus center: 18005216274 mfax ? : rmfax0@email.sps.mot.com touchtone 1 6022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 http://sps.motorola.com/mfax/ home page : http://motorola.com/sps/ mc145220/d ? archive informa tion archive informa tion f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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